This invention relates to a semiconductor integrated circuit device and also to a method for manufacturing the same. More particularly, the invention relates to a technique which is suitably applicable to semiconductor integrated circuit devices which include a DRAM (dynamic random access memory) provided with a memory cell having a stacked capacitor structure wherein an information storage capacitor is arranged above a MISFET for memory cell selection.
The recent DRAM with a great capacity usually has a stacked capacitor structure, wherein an information storage capacitor is arranged above a memory cell selection MISFET, in order to compensate for a storage charge reduction of an information storage capacitor as will be caused by the miniaturization of the memory cells.
The information storage capacitor having the stacked capacitor structure is formed by successively superposing a storage electrode (lower electrode), a capacity insulating film(dielectric film), and a plate electrode (upper electrode). The storage electrode of the information storage capacitor is connected with one of the semiconductor regions (source region, drain region) of a memory selection MISFET of the n channel type. The plate electrode is constituted as a common electrode for a plurality of memory cells and is supplied with a given fixed potential (plate potential).
The other semiconductor region (source region, drain region) of the memory cell selection MISFET is, in turn, connected to bit line in order to a permit data to be written in and read out. The bit line is provided between the MISFET for memory cell selection and the information storage capacitor or above the information storage capacitor. The structure wherein the information storage capacitor is provided above the bit lines is called a xe2x80x9ccapacitor over bitlinexe2x80x9d (COB) structure.
A DRAM having such a COB structure is described, for example, in Japanese Laid-open Patent Application No. 7-122654 (corresponding to a U.S. patent application Ser. No. 08/297,039, assigned to Hitachi Ltd.), and Japanese Laid-open Patent Application No. 7-106437.
The DRAM disclosed in the Japanese Laid-open Patent Application No. 7-122654 includes bit lines which are formed of a polysilicon film (or polycide film) formed above the MISFET for memory cell selection wherein a gate electrode (word line) is formed of a built-up film (polycide film) of a polysilicon film and a tungsten silicide (WSix) film. An information storage capacitor which includes a storage electrode formed of a polysilicon, a capacitance insulating film constituted of a built-up film of a silicon oxide film and a silicon nitride film, and a plate electrode formed of a polysilicon film are provided above the bit lines. In addition, a common source line made of a first layer made of an Al (aluminium) film and a word line for a shunt are formed over the information storage capacitor.
The DRAM set out in the Japanese Laid-open Patent Application No. 7-106437 includes bit lines made of a polysilicide film and formed on the MISFET for memory cell selection whose gate electrode (word line) is made of a polysilicon film. The storage electrode or plate electrode of the information storage capacitor disposed above the bit lines and the first interconnection layer of a peripheral circuit are both formed of a metal material (e.g. Pt). Thus, the step of forming the electrode of the information storage capacitor and the step of forming the metallic interconnection of the peripheral circuit are performed commonly to simplify the manufacturing process.
The DRAM having the COB structure includes a gate electrode (word line) formed of polysilicon or polycide which has a resistance greater than metallic materials such as Al or W, so that a metallic interconnection (a word line for shunt) for backing the gate electrode is formed above the information storage capacitor, thereby reducing the delay of the gate. Since the bit line is constituted of polycide which is unable to simultaneously connect n-type and p-type semiconductor regions therewith, it is not possible to use a common interconnection for the bit lines and the peripheral circuit. To avoid this, the number of interconnection layers for both the memory arrays and the peripheral circuit increases, thus presenting a problem of increasing the number of manufacturing steps.
The common use of the interconnections for the bit lines and the peripheral circuit is not possible, so that the first interconnection layer of the peripheral circuit has to be formed as an upper layer relative to the bit lines. This causes a great aspect ratio (diameter/depth) of a connection hole for connecting the first interconnection layer and the MISFET""s of the peripheral circuit, with the attendant problem that the formation of the connection hole becomes difficult and it also becomes difficult to embed or fill an interconnection material in the connection hole.
Where the gate electrode (word line) is formed of polysilicon or polycide with a high resistance, it is not possible to increase the number of memory cells capable of connection with one word driver or sense amplifier. More particularly, in order to reduce the delay of the gate, an increasing number of word drivers or sense amplifiers are necessary for connection to a given number of memory cells, so that there arises the problem that the chip size has to be increased, resulting in the lowering in degree of integration.
An object of the invention is to provide a technology capable of simplifying a process of manufacturing a DRAM having the COB structure.
Another object of the invention is to provide a technology for achieving a high-speed DRAM having the COB structure.
A further object of the invention is to provide a technology for achieving a high performance DRAM having the COB structure.
A still further object of the invention is to provide a technology for achieving a highly integrated DRAM having the COB structure.
The above and other objects, and features of the invention will become apparent from the description with reference to the accompanying drawings.
Typical inventions in this application are summarized below.
The semiconductor integrated circuit device according to one aspect of the inventions comprises a DRAM which includes a memory cell constituted of a MISFET for memory cell selection and an information storage capacitor formed on the MISFET, wherein a sheet resistance of a gate electrode of the MISFET for memory cell selection and a word line connected thereto, and a sheet resistance of a bit line connected to one of a source region and a drain region of the MISFET for memory cell selection, are, respectively, 2 xcexa9/xe2x96xa1 or below.
In the above one aspect of the invention, it is preferred that the sheet resistance of the gate electrode of the MISFET for memory cell selection and the word line connected thereto, and the sheet resistance of the bit line connected to one of a source region and a drain region of the MISFET for memory cell selection, are, respectively, 1 xcexa9/xe2x96xa1 or below.
It is also preferred that the gate electrode of the MISFET and the word line connected thereto are, respectively, made of a built-up film comprising, at least, a polysilicon film and a metallic film or a metal silicide film formed on the polysilicon film.
Preferably, the bit line is arranged above or over the MISFET for memory cell selection, and the information storage capacitor is arranged above or over the bit line.
The bit line should preferably be constituted of a built-up film which comprises, at least, a polysilicon film and a metallic film or a metal silicide film formed on the polysilicon film.
The sheet resistance of the interconnection formed on the information storage capacitor should preferably be equal to or smaller than that of the bit line.
A given interconnection layer of a peripheral circuit of the DRAM in the semiconductor integrated circuit device of the invention should preferably include an interconnection formed in the same manufacturing step as the gate electrode of the memory cell selection MISFET and the word line connected thereto.
A given interconnection layer of a peripheral circuit of the DRAM in the semiconductor integrated circuit device of the invention should preferably include an interconnection formed in the same manufacturing step as the bit line.
Preferably, the peripheral circuit of the DRAM is provided with a resistor which is formed in the same manufacturing step as the bit line.
According to a further aspect of the invention, there is also provided a semiconductor integrated circuit device which comprises a DRAM having a memory cell which includes a MISFET for memory cell selection and an information storage capacitor formed on the MISFET, wherein the information storage capacitor has a storage electrode whose sheet resistance is 2 xcexa9/xe2x96xa1 or below.
In this further aspect, it is preferred that an interconnection formed in the same manufacturing step as the storage electrode of the information storage capacitor is formed in a given interconnection layer of a peripheral circuit of the DRAM.
It is also preferred that the peripheral circuit of the DRAM is provided with a resistor which is formed in the same manufacturing step as the storage electrode of the information storage capacitor.
According to a further aspect of the invention, there is provided a semiconductor integrated circuit device which comprises a DRAM having a memory cell which includes a MISFET for memory cell selection and an information storage capacitor formed on the MISFET, wherein the information storage capacitor has a plate electrode whose sheet resistance is 2 xcexa9/xe2x96xa1 or below.
In the further aspect, it is preferred that an interconnection formed in the same manufacturing step as the plate electrode of the information storage capacitor is formed in a given interconnection layer of a peripheral circuit of the DRAM.
Preferably, the peripheral circuit of the DRAM is provided with a resistor which is formed in the same manufacturing step as the plate electrode of the information storage capacitor.
According to a still further aspect of the invention, there is provided a method for manufacturing a semiconductor integrated circuit device which comprises a DRAM which includes a memory cell constituted of a MISFET for memory cell selection and an information storage capacitor formed thereon, the method comprising the steps of:
(a) forming a word line connected to a gate electrode of the MISFET for memory cell selection on a semiconductor substrate wherein the word line has a sheet resistance of 2 xcexa9/xe2x96xa1 or below; and
(b) forming a bit line connected to one of a source region and a drain region of the MISFET for memory cell selection on the gate electrode of the MISFET for memory cell selection and the word line connected thereto and having a sheet resistance of 2 xcexa9/xe2x96xa1 or below.
Preferably, the method further comprises the step of forming an information storage capacitor on the bit line wherein at least one of a storage electrode and a plate electrode of the capacitor has a sheet resistance of 2 xcexa9/xe2x96xa1 or below.
It is also preferred that the method further comprises the step of forming an interconnection having a sheet resistance equal to or smaller than the sheet resistance of the bit line, on the capacitor.
In the method according to the above aspect of the invention, a first interconnection layer of a peripheral circuit is formed in the step (a) or (b).
Moreover, in the step of forming the storage electrode or the plate electrode of the information storage capacitor, it is preferred to form a second interconnection layer of the peripheral circuit.
Preferably, a third interconnection layer of the peripheral circuit is formed over the capacitor in the step of forming an interconnection and a Y selection line built up on the plate electrode of the information storage capacitor.
Preferably, the method of the invention should further comprise the step of simultaneously forming at least two connection holes among a first connection hole connecting the third interconnection layer and the second interconnection layer, a second connection hole connecting the third interconnection layer and the first interconnection layer, a third connection hole connecting the second interconnection layer and the first interconnection layer, and a fourth connection hole connecting the third interconnection layer, the second interconnection layer and the first interconnection layer, wherein the at least two connection holes are formed in a layer of insulating film for insulating the third interconnection layer and the second interconnection layer from each other.
It is also preferred that a dummy interconnection is formed below the first connection hole connecting the third interconnection layer and the second interconnection layer in the same step as the first interconnection layer.
Moreover, a dummy interconnection is preferably formed on the way of the second connection hole connecting the third interconnection layer and the first interconnection layer in the same step as the second interconnection layer.
Preferably, a dummy interconnection is preferably formed above the third connection hole connecting the second interconnection layer and the first interconnection layer in the same step as the third interconnection layer.
A method for manufacturing a semiconductor integrated circuit device according to a further aspect of the invention is characterized by forming a DRAM having a memory cell constituted of a MISFET for memory cell selection and an information storage capacitor formed on the MISFET, and a logic LSI on the same plane of a semiconductor substrate, wherein a sheet resistance of a gate electrode of the MISFET and a word line connected thereto, and a sheet resistance of a bit line are, respectively, 2 xcexa9/xe2x96xa1 or below, and a given interconnection of the logic LSI is formed in the same step as the gate electrode of the MISFET and the word line connected thereto or the bit line.
Preferably, the above method further comprises forming, on the bit line, an information storage capacitor having a storage electrode and a plate electrode at least one of which has a sheet resistance of 2 xcexa9/xe2x96xa1 or below, and forming the given interconnection of the logic LSI simultaneously at the step of forming the storage electrode or the plate electrode.
According to a further aspect of the invention, there is provided a method for manufacturing a semiconductor integrated circuit device, the method comprising the steps of:
providing a semiconductor substrate having first and second portions on the main surface thereof;
depositing a first conductor layer on the first and second portions and subjecting the first conductor layer to patterning to form a first interconnection on the first portion and a second interconnection on the second portion;
forming a first insulating film over the semiconductor substrate to cover the first and second interconnections;
depositing a second conductor layer over the first and second portions and patterning the second conductor layer to form a third interconnection as superposed on the first interconnection via the first insulating film over the first portion and a fourth interconnection as superposed on the second interconnection via the first insulating film over the second portion;
forming a second insulating film over the semiconductor substrate to cover the third and fourth interconnections therewith;
forming a first connection hole in a portion of the first portion where the first and third interconnections are superposed so that the first interconnection is exposed on the surface thereof via the second insulating film, the third interconnection and the first insulating film, and also a second connection hole in a portion of the second portion where the second and fourth interconnections are superposed so that the second interconnection is exposed on the surface thereof via the second insulating film, the fourth interconnection and the first insulating film;
filling a third conductor layer in the first and second connection holes; and
depositing a fourth conductor layer over the first and second portions and patterning the fourth conductor layer to form a fifth interconnection in the first portion to cover the first connection hole and a sixth interconnection in the second portion to cover the second connection hole, wherein the third conductor layer in the first connection layer electrically connects the first, third and fifth interconnections therewith and the third conductor layer in the second connection hole electrically connects the second and fourth interconnections therewith and wherein the sixth interconnection protects the third conductor layer in the second connection hole at the time of the patterning of the fourth conductor layer.
According to a further aspect of the invention, there is provided a method for manufacturing a semiconductor integrated circuit device, the method comprising the steps of:
providing a semiconductor substrate having first and second portions on the main surface thereof;
depositing a first conductor layer on the first and second portions and subjecting the first conductor layer to patterning to form a first interconnection on the first portion and a second interconnection on the second portion;
forming a first insulating film over the semiconductor substrate to cover the first and second interconnections;
depositing a second conductor layer on the first and second portions and patterning the second semiconductor layer to form a third interconnection as superposed on the first interconnection via the first insulating film over the first portion and a fourth interconnection as superposed on the second interconnection via the first insulating film over the second portion;
forming a second insulating film over the semiconductor substrate to cover the third and fourth interconnections therewith;
forming a first connection hole in a portion of the first portion where the first and third interconnections are superposed so that the first interconnection is exposed on the surface thereof via the second insulating film, the third interconnection and the first insulating film, and also a second connection hole in a portion of the second portion where the second and fourth interconnections are superposed so that the second interconnection is exposed on the surface thereof via the second insulating film, the fourth interconnection and the first insulating film;
filling a third conductor layer in the first and second connection holes; and
depositing a fourth conductor layer over the first and second portions and patterning the fourth conductor layer to form a fifth interconnection in the first portion to cover the first connection hole and also a sixth interconnection in the second portion to cover the second connection hole, wherein the third conductor layer in the first connection layer electrically connects the first, third and fifth interconnections therewith and the third conductor layer in the second connection hole electrically connects the second and fourth interconnections therewith.
According to a further aspect of the invention, there is provided a method for manufacturing a semiconductor integrated circuit device, the method comprising the steps of:
providing a semiconductor substrate having first and second portions on the main surface thereof;
depositing a first conductor layer on the first and second portions and subjecting the first conductor layer to patterning to form a first interconnection on the first portion and a second interconnection on the second portion;
forming a first insulating film over the semiconductor substrate to cover the first and second interconnections;
depositing a second conductor layer on the first and second portions and patterning the second semiconductor layer to form a third interconnection as superposed on the first interconnection over the first portion;
forming a second insulating film over the semiconductor substrate to cover the third interconnection therewith;
forming a first connection hole in the first portion so that the second interconnection is exposed on the surface thereof and also a second connection hole in the second portion so that the second interconnection is exposed on the surface thereof; and
depositing a third conductor layer over the first and second portions and patterning the third conductor layer to form a fourth interconnection in the first portion to cover the first connection hole and also a fifth interconnection in the second portion to cover the second connection hole, wherein the first interconnection is superposed with the first connection hole on a plane.
According to a further aspect of the invention, there is provided a method for manufacturing a semiconductor integrated circuit device which comprises a plurality of memory cells including MISFET""s for memory cell selection and information storage capacitors connected in series, a plurality of memory cell arrays having a plurality of word lines and a plurality of bit lines mutually extending in parallel to each other, and peripheral circuits located between the plural memory cell arrays, the method comprising the steps of:
providing a semiconductor substrate having a first portion wherein memory cell arrays are formed and a second portion wherein peripheral circuits are formed;
forming a first conductor layer over the semiconductor substrate and patterning the first conductor layer to form a plurality of first interconnections to form bit lines in the first portion and second and third interconnections in the second portion;
forming a first insulating film on the first, second and third interconnections;
forming a second conductor layer on the first insulating film and patterning the second conductor layer to form one of the electrodes of each information storage capacitor independently for each memory cell;
forming a third conductor layer on the one electrode of the information storage capacitor and patterning the third conductor to form the other electrode of the information storage capacitor commonly used for the plurality of memory cells in the first portion and to form a fourth interconnection on the second interconnection in the second portion;
forming a second insulating film on the other electrode of the information storage capacitor and the fourth interconnection; and
forming a first connection hole in the second portion so that the fourth interconnection is exposed on the surface thereof in the second insulating film and also a second connection hole so that the third interconnection is exposed on the surface thereof in the second insulating film, wherein the second interconnection is positioned below the first connection hole.